A frequency divider counter generally provides an output clock signal having a frequency that is lower than a frequency of an input clock signal. Frequency divider counters are commonly used to step down a system clock frequency for certain circuits in a system that require a lower operating frequency than the system clock frequency.
The frequency divider counter receives a sequence of binary numbers starting at a predetermined value and counts up or down by one until a predetermined final value is reached. In some N+1 frequency divider counters, if the counter is counting an odd number of cycles of the input clock signal, the stepped down output clock signal will not have a 50 percent duty cycle. For example, if N+1 is equal to 11, one phase of the output clock signal will include 6 clock cycles of the input clock signal, and the other phase of the output clock signal will include 5 clock cycles of the input clock signal. This results in a duty cycle that is different than the desired fifty percent duty cycle for the output clock signal. In some applications, a fifty percent duty cycle is required for proper operation of the circuit receiving the stepped down clock signal. In those N+1 frequency divider counters that do have a fifty percent duty cycle for odd values of N+1, added complexity is required for the case when N is equal to zero.